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CDB5345 Evaluation Board for CS5345
Features
Single-ended Analog Inputs Single-ended Analog Outputs CS8406 S/PDIF Digital Audio Transmitter Header for Optional External Software Configuration of CS5345 Header for External PCM Serial Audio I/O 3.3 V Logic Interface Pre-defined Software Scripts Demonstrates Recommended Layout and Grounding Arrangements Windows(R) Compatible Software Interface to Configure CS5345 and Inter-board Connections
Description
The CDB5345 evaluation board is an excellent means for evaluating the CS5345 ADC. Evaluation requires an analog signal source and analog/digital analyzer, and power supplies. A Windows(R) PC compatible computer must be used to evaluate the CS5345. System timing for the IS, Left-Justified and Right-Justified interface formats can be provided by the CS5345, the CS8406, or by a PCM I/O stake header with an external source connected. RCA phono jacks are provided for the CS5345 analog inputs and outputs. Digital data input is available via RCA phono or optical connectors to the CS8406. The Windows(R) software provides a GUI to make configuration of the CDB5345 easy. The software communicates through the PC's serial port to configure the control port registers so that all features of the CS5345 can be evaluated. The evaluation board may also be configured to accept external timing and data signals for operation in a user application during system development.
ORDERING INFORMATION CDB5345
I
Evaluation Board
Passive Input Filter Active Input Filter Microphone Input M U X
Active Output Filter Test Points
CS5345
Master Clock
Canned Oscillator
Header Control Port Interface FPGA
Sub-clocks and Data
CS8406
Cirrus Logic, Inc. www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
FEB `05 DS658DB1
CDB5345
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ............................................................................................................... 4 1.1 Power ................................................................................................................................. 4 1.2 Grounding and Power Supply Decoupling ......................................................................... 4 1.3 CS5345 Audio ADC ........................................................................................................... 4 1.4 CS8406 Digital Audio Transmitter ...................................................................................... 4 1.5 FPGA ................................................................................................................................. 4 1.6 Canned Oscillator .............................................................................................................. 4 1.7 External Control Headers ................................................................................................... 5 1.8 Analog Inputs ..................................................................................................................... 5 1.9 Analog Outputs .................................................................................................................. 5 1.10 Serial Control Port ............................................................................................................ 5 1.11 USB Control Port ............................................................................................................. 5 2. SYSTEM CLOCKS AND DATA ................................................................................................ 6 2.1 Clock Routing ..................................................................................................................... 6 2.2 Data Routing ...................................................................................................................... 6 3. PC SOFTWARE CONTROL ..................................................................................................... 7 3.1 CDB5345 Controls Tab ...................................................................................................... 7 3.2 Register Maps Tab ............................................................................................................. 8 3.3 Pre-Configured Script Files ................................................................................................ 8 3.3.1 Oscillator Clock - ADC Ch 1 In to In to SPDIF & PGA Out ................................... 8 3.3.2 Oscillator Clock - ADC Ch 2 In to In to SPDIF Out ............................................... 9 4. FPGA REGISTER QUICK REFERENCE ............................................................................... 10 5. FPGA REGISTER DESCRIPTION ......................................................................................... 11 6. CDB CONNECTORS, JUMPERS, AND SWITCHES ............................................................. 13 7. CDB BLOCK DIAGRAM ..................................................................................................... 15 8. CDB SCHEMATICS ............................................................................................................... 16 9. CDB LAYOUT ........................................................................................................................ 24 10. REVISION HISTORY ............................................................................................................ 27
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LIST OF FIGURES
Figure 1. CDB5345 Controls Tab.................................................................................................... 7 Figure 2. Register Maps Tab........................................................................................................... 8 Figure 3. Block Diagram................................................................................................................ 15 Figure 4. CS5345 .......................................................................................................................... 16 Figure 5. Analog Inputs ................................................................................................................. 17 Figure 6. Analog Outputs .............................................................................................................. 18 Figure 7. S/PDIF Output................................................................................................................ 19 Figure 8. Control Port.................................................................................................................... 20 Figure 9. FPGA ............................................................................................................................. 21 Figure 10. Discrete Clock Routing and Level Shifting................................................................... 22 Figure 11. Power........................................................................................................................... 23 Figure 12. Silk Screen................................................................................................................... 24 Figure 13. Topside Layer .............................................................................................................. 25 Figure 14. Bottom side Layer ........................................................................................................ 26
LIST OF TABLES
Table 1. MCLK Source.................................................................................................................. 11 Table 2. Subclock Source ............................................................................................................. 12 Table 3. CS8406 SDIN Source ..................................................................................................... 12 Table 4. System Connections ....................................................................................................... 13 Table 5. System Jumper Settings ................................................................................................. 14 Table 6. Revision History .............................................................................................................. 27
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1. SYSTEM OVERVIEW
The CDB5345 evaluation board is an excellent means for evaluating the CS5345 ADC. Analog and digital audio signal interfaces are provided, an on-board FPGA is used for easily configuring the evaluation platform, and a 9-pin serial cable is included for use with the supplied Windows(R) configuration software. The CDB5345 schematic set is shown in Figures 4 through 11. The CDB5345 is assembled on the printed wire board designed for the CDB4245, with a number of components un-populated. These un-populated components have been removed from the included schematic set for clarity. For a complete schematic set, see the CDB4245 data sheet.
1.1
Power
Power must be supplied to the evaluation board through the red +5.0 V binding post. On-board regulators provide 3.3 V, 2.5 V, and 1.8 V supplies. Appropriate supply levels for powering VA, VD, VLS, and VLC are set by a series of jumpers (see Table 5 on page 14). All voltage inputs must be referenced to the single black binding post ground connector (see Table 4 on page 13). WARNING: Please refer to the CS5345 data sheet for allowable voltage levels.
1.2
Grounding and Power Supply Decoupling
The CS5345 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 3 on page 15 provides an overview of the connections to the CS5345. Figure 12 on page 24 shows the component placement. Figure 13 on page 25 shows the top layout. Figure 14 on page 26 shows the bottom layout. The decoupling capacitors are located as close to the CS5345 as possible. Extensive use of ground plane fill in the evaluation board yields large reductions in radiated noise.
1.3
CS5345 Audio ADC
A complete description of the CS5345 is included in the CS5345 product data sheet. The required configuration settings of the CS5345 are made in its control port registers, accessible through the CS5345 tab of the Cirrus Logic FlexGUI software. Clock and data source selections are made through the control port of the FPGA. Basic routing selections can be made using the CS5345 Controls tab in the GUI software application. Advanced options are accessible through the Board Configuration sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI software. Refer to the FPGA register descriptions sections beginning on page 11.
1.4
CS8406 Digital Audio Transmitter
A complete description of the CS8406 transmitter (Figure 7 on page 19) and a discussion of the digital audio interface are included in the CS8406 data sheet. The CS8406 converts the PCM data generated by the CS5345 to the standard S/PDIF data stream. The CS8406 can operate in either master or slave mode, accepts 128 Fs, 256 Fs, 384 Fs, and 512 Fs master clocks on the OMCK input pin, and can operate in the Left-Justified, IS, Right-Justified 16-bit, and RightJustified 24-bit interface formats. The most common operations of the CS8406 may be controlled via the CDB5345 Controls tab in the GUI software application. Advanced options are accessible through the CS8406 sub-tab on the Register Maps tab of the Cirrus Logic FlexGUI software.
1.5
FPGA
The FPGA handles both clock and data routing on the CDB5345. Clock and data routing selections made via the CDB5345 Controls tab in the GUI will be handled by the FPGA with no user intervention required. For advanced information regarding the internal registers and operation of the FPGA, see sections 4 and 5 beginning on page 10.
1.6
Canned Oscillator
A canned oscillator, Y1, is available to provide a master clock source to the CDB5345.
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The oscillator is mounted in pin sockets, allowing easy removal or replacement. The board is shipped with a 12.2880 MHz crystal oscillator populated.
1.7
External Control Headers
The evaluation board has been designed to allow interfacing with external systems via the headers J10, and J17. The 8-pin, 2 row header, J10, provides access to the serial audio signals required to interface to the serial audio port of the CS5345 with a DSP (see Figure 10 on page 22). The direction of the signals on header J10 can be configured using the controls located within the Board Controls group box on the CDB5345 Controls tab in the provided GUI software. The 15-pin, 3 row header, J17, allows the user bidirectional access to the SPI/I2C control signals by simply removing all the shunt jumpers from the "PC" position. The user may then choose to connect a ribbon cable to the "EXTERNAL CONTROL" position. A single "GND" row for the ribbon cable's ground connection is provided to maintain signal integrity. Two unpopulated pull-up resistors are also available should the user choose to use the CDB for the I2C power rail.
1.8
Analog Inputs
RCA connectors supply the CS5345 analog inputs through single-ended, unity gain, active or passive circuits. Refer to the CS5345 data sheet for the ADC full-scale level. A 4-pin CD-ROM type header is provided for easily connecting the analog outputs from a CD-ROM drive to the analog inputs of the CS5345.
1.9
Analog Outputs
The CS5345 PGA analog outputs are routed through a two-pole active filter. The output of the filter is connected to RCA jacks for easy evaluation.
1.10 Serial Control Port
A graphical user interface is included with the CDB5345 to allow easy manipulation of the registers in the CS5345, CS8406, and FPGA. See the device-specific data sheets for the CS5345 and CD8406 internal register descriptions. The internal register map for the FPGA is located in section 4 on page 10. Connecting a cable to the RS-232 connector (J42) and launching the Cirrus Logic FlexGUI software (FlexLoader.exe) will enable the CDB5345. Refer to "PC Software Control" on page 7 for a description of the Graphical User Interface (GUI).
1.11 USB Control Port
The USB control port connector (J37) is currently unavailable.
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2. SYSTEM CLOCKS AND DATA
The CDB5345 implements comprehensive clock routing capabilities. Configuration of the clock routing can be easily achieved using the controls within the Board Controls group box on the CDB5345 Controls tab in the GUI software application.
2.1
Clock Routing
The master clock signal (MCLK) may be sourced from the canned oscillator (Y1) or the PCM1 I/O header (J10) The sub-clock signals (SCLK and LRCK) may be sourced from the CS5345 in master mode, the CS8406 in master mode, or the PCM1 I/O header. Clock routing configuration is achieved using the MCLK Source and Subclock Source controls within the Board Controls group box on the CDB5345 Controls tab in the GUI software application.
2.2
Data Routing
The serial data output of the CS5345 is routed to both the CS8406 S/PDIF transmitter and the PCM1 I/O header. No user configuration of the serial data routing is required.
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3. PC SOFTWARE CONTROL
The CDB5345 is shipped with a Microsoft Windows(R) based graphical user interface which allows control over the CS5345, CS8406, and FPGA. The board control software communicates with the CDB5345 over the RS-232 interface using the PC's COM1 port. To use the board control software, the contents of the included CD-ROM should first be copied to a directory on the PC's local disk. If applied, the Read Only attribute should be removed from all files. Once the appropriate cable has been connected between the CDB5345 and the host PC, load FlexLoader.exe from the Software directory. When the software loads, all devices will be reset to their default reset state. The GUI's File menu provides the ability to save and load script files containing all of the register settings. Pre-configured script files are provided for basic functionality. Refer to "Pre-Configured Script Files" on page 8 for details.
3.1
CDB5345 Controls Tab
The CDB5345 Controls tab provides a high-level intuitive interface to many of the configuration options of the CS5345 and CDB5345. The controls within the ADC/PGA Controls group box control the internal registers of the CS5345. The controls within the Board Controls group box control the board level clock and data routing on the CDB5345.
Figure 1. CDB5345 Controls Tab
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3.2 Register Maps Tab
The Register Maps tab provides low level control over the register level settings of the CS5345, CS8406, and FPGA. Each device is displayed on a separate tab. Register values can be modified bit-wise or bytewise. For bit-wise, click the appropriate push button for the desired bit. For byte-wise, the desired hex value can be typed directly in the register address box in the register map.
Figure 2. Register Maps Tab
3.3
Pre-Configured Script Files
Pre-configured script files are provided with the CDB5345 to allow easy initial board bring-up. The board configurations stored within these files are described in sections 3.3.1 - 3.3.2.
3.3.1
Oscillator Clock - ADC Ch 1 In to In to SPDIF & PGA Out
Using the pre-configured script file named "Oscillator Clock - ADC Ch 1 In to SPDIF & PGA Out.txt", an analog input signal applied to channel 1 of the CS5345 input multiplexer will be digitized by the ADC, transmitted in S/PDIF format by the CS8406, and will be output through the active output filter and RCA jacks. The canned oscillator is the source of MCLK. The CS5345 is the sub-clock master to the CS8406 and the PCM1I/O header.
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3.3.2 Oscillator Clock - ADC Ch 2 In to In to SPDIF Out
Using the pre-configured script file named "Oscillator Clock - ADC Ch 2 In to SPDIF Out.txt", an analog input signal applied to channel 2 of the CS5345 input multiplexer will be digitized by the ADC and transmitted in S/PDIF format by the CS8406. No signal will be output through the active output filter and RCA jacks. The canned oscillator is the source of MCLK. The CS5345 is the sub-clock master to the CS8406 and the PCM1I/O header.
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4. FPGA REGISTER QUICK REFERENCE This table shows the register names and their associated default values.
Addr
01h
Function
Code Rev. ID
7
Rev7 x
6
Rev6 x
5
Rev5 x Reserved 1 Reserved 0 Reserved 0 Reserved 0
4
Rev4 x Reserved 0 Reserved 1 Reserved 0 CS8406 1
3
Rev3 x Reserved 0 Reserved 0 Reserved 0 Reserved 0
2
Rev2 x Reserved 0 Reserved 0 Reserved 0 Reserved 0
1
Rev1 x Reserved 0 SUBCLK1 0 Reserved 0 Reserved 0
0
Rev0 x MCLK 0 SUBCLK0 1 Reserved 0 Reserved 1
02h
MCLK Source
Reserved Reserved 0 0
03h
Subclock Source Reserved
Reserved Reserved 0 0
04h
Reserved Reserved 0 0
05h
Transmitter SDIN Source
Reserved Reserved 0 0
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5. FPGA REGISTER DESCRIPTION 5.1 CODE REVISION ID - ADDRESS 01H
7 Rev7 6 Rev6 5 Rev5 4 Rev4 3 Rev3 2 Rev2 1 Rev1 0 Rev0
Function: Identifies the revision of the FPGA code. This register is Read-Only.
5.2
MCLK SOURCE CONTROL - ADDRESS 02H
6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 MCLK
7 Reserved
5.2.1
MCLK SOURCE (BIT 0)
Default = 0 Function: This bit selects the source of the CS5345 MCLK signal. Table 1 shows the available settings.
Table 1. MCLK Source
MCLK
0 1
MCLK Source
Canned Oscillator M1 position on PCM1 I/O Header
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5.3 SUBCLOCK SOURCE CONTROL - ADDRESS 03H
6 Reserved 5 Reserved 4 Reserved 3 Reserved 2 Reserved 1 SUBCLK1 0 SUBCLK0
7 Reserved
5.3.1
SUBCLOCK SOURCE (BITS 1:0)
Default = 01 Function: This bit selects the source of the CS5345 SCLK and LRCK signals. Table 2 shows the available settings.
Table 2. Subclock Source
SUBCLOCK1
0
SUBCLOCK
0
Subclock Source
- CS5345 is Master - CS8406 is Slave to CS5345 - PCM I/O Header Subclocks are Output from CS5345 - CS5345 is Slave to CS8406 - CS8406 is Master - PCM I/O Header Subclocks are Output from CS8406 - CS5345 is Slave to Header - CS8406 is Slave to Header - PCM I/O Header Subclocks are an Input Reserved
0
1
1
0
1
1
5.4
TRANSMITTER SDIN SOURCE CONTROL - ADDRESS 05H
6 Reserved 5 Reserved 4 CS8406 3 Reserved 2 Reserved 1 Reserved 0 Reserved
7 Reserved
5.4.1
CS8406 SDIN SOURCE (BIT 4)
Default = 0 Function: These bit selects the source of the CS8406 SDIN signal. Table 3 shows the available settings.
Table 3. CS8406 SDIN Source
CS8406
0 1
CS8406 SDIN Source
Reserved CS5345 SDOUT
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6. CDB CONNECTORS, JUMPERS, AND SWITCHES
Reference Designator INPUT/OUTPUT
J1 J2 J15 OPT2 J42 J37 J10 J17 J36 J18 S2 S1 J38 J39 J40 J41 J21 J34 J14 J16 Input Input Output Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input Input Input Output
CONNECTOR
+5V GND S/PDIF TX S/PDIF TX RS232 I/O USB I/O PCM1 I/O CONTROL MICRO JTAG FPGA-JTAG MICRO RESET PROGRAM FPGA PINA PINB AINA AINB MICIN1 MICIN2 AOUTA AOUTB
SIGNAL PRESENT +5.0 V Power Supply Ground Reference CS8406 digital audio output via coaxial cable CS8406 digital audio output via optical cable Serial connection to PC for SPI / I2C control port signals USB connection to PC for SPI / I2C control port signals. Not Available. I/O for Serial Audio Clocks & Data I/O for external SPI / I2C control port signals. I/O for programming the micro controller (U46). I/O for programming the FPGA (U35). Reset for the micro controller (U46). Reset for the FPGA (U35). RCA phono jacks for analog input signal to CS5345. Passive input filter. RCA phono jacks for analog input signal to CS5345. Active input buffer. 1/8" TRS jacks for microphone input. RCA phono jacks for PGA analog outputs. Active output buffer.
Table 4. System Connections
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JUMPER
J3
PURPOSE
Selects the source of voltage for the VLC supply.
POSITION
+1.8 V +2.5 V +3.3 V +5 V* +3.3 V +5 V* +1.8 V +2.5 V +3.3 V +5 V* +3.3 V +5 V* Line Input* Mic Input
FUNCTION SELECTED Voltage source is +1.8 V regulator. Voltage source is +2.5 V regulator. Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. Voltage source is +1.8 V regulator. Voltage source is +2.5 V regulator. Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. Voltage source is +3.3 V regulator. Voltage source is +5 V regulator. Select RCA input multiplexer as source. Select TRS inputs as source.
J4 J5
Selects the source of voltage for the VD supply Selects the source of voltage for the VLS supply.
J6 J19 J20 J22 - J33
Selects the source of voltage for the VA supply Select the input type for channel 4 of the CS5345 ADC input multiplexer.
Maps the passive and active input circuits Passive Filter* Passive filter mapped to input MUX channel. to the CS5345 input multiplexer channels. Active Filter Active filter mapped to input MUX channel. *Default factory settings Table 5. System Jumper Settings
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Passive Input Filter Active Output Filter M U X Test Points
7. CDB BLOCK DIAGRAM
Active Input Filter
Microphone Input
CS5345
Master Clock
Canned Oscillator
Header
Control Port Interface FPGA
Sub-clocks and Data
CS8406
CDB5345
Figure 3. Block Diagram
15
CDB5345
8. CDB SCHEMATICS
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Figure 4. CS5345
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Figure 5. Analog Inputs
17
18
CDB5345
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Figure 6. Analog Outputs
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Figure 7. S/PDIF Output
19
20
CDB5345
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Figure 8. Control Port
CDB5345
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Figure 9. FPGA
21
22
CDB5345
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Figure 10. Discrete Clock Routing and Level Shifting
CDB5345
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Figure 11. Power
23
CDB5345
9. CDB LAYOUT
24
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Figure 12. Silk Screen
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Figure 13. Topside Layer
25
26
CDB5345
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Figure 14. Bottom side Layer
CDB5345
10. REVISION HISTORY
Revision DB1 Date February 2005 Initial Release
Table 6. Revision History
Changes
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Windows is a registered trademark of Microsoft Corporation.
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